In recent years, semiconductor devices have been characterized by continuous reductions of their overall dimensions as well as a continuous increase of the integration density of elemental transistor structures comprised in these devices.
At present, there is the need for fabricating memory devices on semiconductors having submicron dimensions integrating non-volatile memory cells (e.g., floating gate cells) with circuitry comprising elemental transistor structures of the CMOS type.
While completely submicron elemental transistor structures of the CMOS type are currently available, there is still a need for suitably designed memory cells having reduced dimensions.
A traditional floating gate memory cell is schematically shown in FIG. 1 and globally indicated with 1. In the traditional concept, the memory cell 1, also called double-poly, is formed above a silicon substrate 2. The memory cell 1 includes a first dielectric layer, which, by way of convention and similarity with similar memory cells is also called tunnel layer, and a polysilicon layer 3 formed thereover. The memory cell 1 further includes a polysilicon layer 5 formed over the polysilicon layer 3, with a further dielectric layer 4 formed therebetween.
In particular, in the double-poly memory cell 1, the first polysilicon layer 3 defines a floating gate of the cell and, during the operation, allows storing electric charges suitable for defining the state of the memory cell 1 (i.e., a logic state 0 or 1).
However, during the integration process with submicron CMOS transistors, the double-poly memory cells 1 show some drawbacks.
On one hand, there is sometimes a need for creating memory cells with submicron dimensions, which clashes with the current dimensions of the double-poly memory cells that have reached their physical minimum although remaining too large for submicron applications.
On the other hand, there is sometimes a need to integrate the current fabrication processes of the memory cells with the fabrication processes of the submicron CMOS transistors.
A known solution suitable for reducing the dimensions of the memory cells includes the introduction in the memory cell itself of nanocrystals to form a so-called nanocrystal memory cell.
In particular, in these nanocrystal memory cells, the nanocrystals store electric charges similarly to the floating gate of the double-poly memory cells. In these nanocrystal memory cells, a layer comprising a plurality of nanocrystals is substituted for one of the polysilicon layers.
A prior art solution for fabricating nanocrystal memory cells is described, for example, in U.S. Patent Application Publication 2004/0232478 (“the '478 Application”), which is incorporated herein by this reference. The '478 Application describes how, above a substrate, first and second silicon oxide layers are formed, each containing a plurality of nanocrystals. These oxide layers are alternated by an intermediate dielectric layer, such as a nitride layer.
Such processes of forming memory cells, although meeting the need of reducing the physical dimensions of the memory cells, show some drawbacks.
In particular, the nitride layer present in the memory cells made for the specific physical characteristics can act, in turn, as a trap of electric charges that can function as a further floating gate for the memory cell.
Moreover, during the integration process with submicron CMOS transistors, the oxidations successive to the deposition of the nitride layer can, in some implementations, alter the thickness of the nitride layer. The altered thickness of the nitride layer sometimes cannot be controlled with accuracy and, thus, may be a source of error during the operation of the memory device so-formed. In particular, the nitride layer may generate errors during the storage of the electric charges in the memory cells, under the programming step of the cells themselves, and during the reading of the charges contained and thus of the effective state of these cells.
Further solutions of nanocrystal memory cells have been proposed and shown by way of example in U.S. Pat. No. 5,714,766 and in U.S. Pat. No. 6,784,103, each of which is incorporated herein by this reference. These patents describe how the nanocrystals are incorporated in a semiconductor layer formed between two oxide layers, such as silicon oxide layers.
A further nanocrystal memory cell is shown in the U.S. Patent Application Publication No. US 2006/0046384 (“the '384 Application”), which is incorporated herein by this reference. The '384 Application discloses a plurality of nanocrystals incorporated in a dielectric layer defining a control gate and located above a tunnel dielectric layer.
Although the nanocrystal memory cells so-formed allow the dimensions of the memory cells to be reduced and avoid using a nitride layer, such nanocrystal memory cells may still show some drawbacks during the processes of integration with CMOS transistors for forming memory devices (i.e., high complexity devices).
In particular, in these high-complexity memory devices, the nanocrystal memory cells are integrated with ultra-submicron CMOS transistors.
As is known, the relative integration processes provide the differentiation of the gate oxides of the submicron CMOS transistors by subjecting the substrate to repeated thermal treatments at high temperatures, such as by employing the In Situ Steam Generation technique (“ISSG”).
Unfortunately, exposing nanocrystals present in the memory cells to high temperatures tends to cause the nanocrystals to arrange themselves in a random, anomalous way that causes irregularities and anomalies. Such irregularities and anomalies may compromise the technical characteristics of the nanocrystals memory cells so-formed and, consequently, deteriorate the performance of the memory device as a whole.
U.S. Pat. No. 6,958,265, which is incorporated herein by this reference, proposes to form semiconductor devices with nanocrystal memory cells by employing an oxidizing barrier layer above the nanocrystals for inhibiting the oxidation of the nanocrystals during the integration process of the device, such as in particular during the thermal treatments used for the forming the gate oxides.
However, this process may form, by means of a specific steam oxidation step, thick gate oxides for the CMOS transistors contained in the device and to partially oxidize a corresponding barrier layer. Therefore ,it may be necessary to provide a final removal step of this barrier layer.